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1. general description the pcf8563 is a cmos 1 real-time clock (rtc) and calendar optimized for low power consumption. a programmable clock output, interrupt output, and voltage-low detector are also provided. all addresses and data are transferred serially via a two-line bidirectional i 2 c-bus. maximum bus speed is 400 kbit/s. the register address is incremented automatically after each written or read data byte. 2. features and benefits ? provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 khz quartz crystal ? century flag ? clock operating voltage: 1.0 v to 5.5 v at room temperature ? low backup current; typical 0.25 ? aat v dd = 3.0 v and t amb =25 ? c ? 400 khz two-wire i 2 c-bus interface (at v dd = 1.8 v to 5.5 v) ? programmable clock output for peripheral devices (32.768 khz, 1.024 khz, 32 hz, and 1hz) ? alarm and timer functions ? integrated osc illator capacitor ? internal power-on reset (por) ? i 2 c-bus slave address: read a3h and write a2h ? open-drain interrupt pin 3. applications ? mobile telephones ? portable instruments ? electronic metering ? battery powered products pcf8563 real-time clock/calendar rev. 9 ? 16 june 2011 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 18 .
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 2 of 45 nxp semiconductors pcf8563 real-time clock/calendar 4. ordering information [1] not to be used for new designs. replacement part is pcf8563t/5. [2] not to be used for new designs. replacement part is pcf8563ts/5. 5. marking table 1. ordering information type number package name description version pcf8563bs/4 hvson10 plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 ? 3 ? 0.85 mm sot650-1 pcf8563p/f4 dip8 plastic dual in-lin e package; 8 leads (300 mil) sot97-1 pcf8563t/5 so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 pcf8563t/f4 [1] so8 plastic small outline package; 8 leads; body width 3.9 mm sot96-1 pcf8563ts/4 [2] tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 pcf8563ts/5 tssop8 plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 table 2. marking codes type number marking code pcf8563bs/4 8563s pcf8563p/f4 pcf8563p pcf8563t/5 8563t pcf8563t/f4 8563t pcf8563ts/4 8563 pcf8563ts/5 8563
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 3 of 45 nxp semiconductors pcf8563 real-time clock/calendar 6. block diagram (1) c osco ; values see ta b l e 3 0 . fig 1. block diagram of pcf8563 001aah658 pcf8563 oscillator 32.768 khz divider clock out interrupt clkout int monitor power on reset watch dog i 2 c-bus interface osci scl sda osco v dd v ss timer function timer_control 0e timer 0f control control_status_1 00 control_status_2 01 clkout_control 0d time vl_seconds 02 minutes 03 hours 04 days 05 alarm function minute_alarm 09 hour_alarm 0a day_alarm 0b weekday_alarm 0c weekdays 06 century_months 07 years 08 (1)
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 4 of 45 nxp semiconductors pcf8563 real-time clock/calendar 7. pinning information 7.1 pinning for mechanical details, see figure 30 . top view. for mechanical details, see figure 31 . fig 2. pin configuration for hvson10 (pcf8563bs) fig 3. pin configuration for dip8 (pcf8563p) top view. for mechanical details, see figure 32 . top view. for mechanical details, see figure 33 . fig 4. pin configuration for so8 (pcf8563t) fig 5. pin configuration for tssop8 (pcf8563ts) 001aaf981 pcf8563bs sda int v ss scl n.c. clkout osco v dd osci n.c. transparent top view 5 6 4 7 3 8 2 9 1 10 terminal 1 index area pcf8563p osci v dd osco clkout int scl v ss sda 001aaf977 1 2 3 4 6 5 8 7 pcf8563t osci v dd osco clkout int scl v ss sda 001aaf975 1 2 3 4 6 5 8 7 pcf8563ts osci v dd osco clkout int scl v ss sda 001aaf976 1 2 3 4 6 5 8 7
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 5 of 45 nxp semiconductors pcf8563 real-time clock/calendar 7.2 pin description [1] the die paddle (exposed pad) is wired to v ss but should not be electrically connected. 8. functional description the pcf8563 contains sixteen 8-bit registers with an auto-incrementing register address, an on-chip 32.768 khz oscillator with one inte grated capacitor, a frequency divider which provides the source clock for the real-time clock (rtc) and calender, a programmable clock output, a timer, an alarm, a voltage-low detector, and a 400 khz i 2 c-bus interface. all 16 registers are designed as addressable 8- bit parallel registers although not all bits are implemented. the first two registers (memory address 00h and 01h) are used as control and/or status registers. the memory addresses 02h through 08h are used as counters for the clock function (seconds up to years counters). address locations 09h through 0ch contain alarm registers which define the conditions for an alarm. address 0dh controls the clkout output frequency. 0eh and 0fh are the timer_control and timer registers, respectively. the seconds, minutes, hour s, days, months, years as well as the minute_alarm, hour_alarm, and day_alarm registers are all coded in binary coded decimal (bcd) format. when one of the rtc registers is written or read, the contents of all time counters are frozen. therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented. 8.1 clkout output a programmable square wave is available at th e clkout pin. operat ion is controlled by the register clkout_control at address 0 dh. frequencies of 32.768 khz (default), 1.024 khz, 32 hz, and 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. clkout is an open-drain output and enabled at power-on. if disabled it becomes high-impedance. table 3. pin description symbol pin description dip8, so8, tssop8 hvson10 osci 1 1 oscillator input osco 2 2 oscillator output int 3 4 interrupt output (open-drain; active low) v ss 45 [1] ground sda 5 6 serial data input and output scl 6 7 serial clock input clkout 7 8 clock output, open-drain v dd 8 9 supply voltage n.c. - 3, 10 not connected; do not connect and do not use as feed through
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 6 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.2 register organization table 4. formatted registers overview bit positions labelled as x are not relevant. bit positions la belled with n should always be written with logic 0; if read they could be either logic 0 or logic 1. after reset, all registers are set according to table 27 . address register name bit 7 6 5 4 3 2 1 0 control and status registers 00h control_status_1 test1 n stop n testc n n n 01h control_status_2 n n n ti_tp af tf aie tie time and date registers 02h vl_seconds vl seconds (0 to 59) 03h minutes x minutes (0 to 59) 04h hours x x hours (0 to 23) 05h days x x days (1 to 31) 06hweekdaysxxxxxweekdays (0 to 6) 07h century_months c x x months (1 to 12) 08h years years (0 to 99) alarm registers 09h minute_alarm ae_m minut e_alarm (0 to 59) 0ah hour_alarm ae_h x hour_alarm (0 to 23) 0bh day_alarm ae_d x day_alarm (1 to 31) 0chweekday_alarmae_wxxxxweekday_alarm (0 to 6) clkout control register 0dhclkout_controlfexxxxxfd[1:0] timer registers 0ehtimer_controltexxxxxtd[1:0] 0fh timer timer[7:0]
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 7 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.3 control registers 8.3.1 register control_status_1 [1] default value. [2] bits labeled as n should alwa ys be written with logic 0. 8.3.2 register control_status_2 [1] bits labeled as n should alwa ys be written with logic 0. [2] default value. table 5. control_status_1 - control and status register 1 (address 00h) bit description bit symbol value description reference 7 test1 0 [1] normal mode must be set to logic 0 during normal operations section 8.9 1 ext_clk test mode 6n 0 [2] unused 5stop0 [1] rtc source clock runs section 8.10 1 all rtc divider chain flip-flops are asynchronously set to logic 0; the rtc clock is stopped (clkout at 32.768 khz is still available) 4n 0 [2] unused 3 testc 0 power-on reset (por) override facility is disa bled; set to logic 0 for normal operation section 8.11.1 1 [1] power-on reset (por) override may be enabled 2to0 n 000 [2] unused table 6. control_status_2 - control and status register 2 (address 01h) bit description bit symbol value description reference 7to5 n 000 [1] unused 4ti_tp0 [2] int is active when tf is active (subject to the status of tie) section 8.3.2.1 and section 8.8 1int pulses active according to ta b l e 7 (subject to the status of tie); remark: note that if af and aie are active then int will be permanently active 3af 0 [2] read: alarm flag inactive section 8.3.2.1 write: alarm flag is cleared 1 read: alarm flag active write: alarm flag remains unchanged 2tf 0 [2] read: timer flag inactive write: timer flag is cleared 1 read: timer flag active write: timer flag remains unchanged 1aie 0 [2] alarm interrupt disabled 1 alarm interrupt enabled 0tie 0 [2] timer interrupt disabled 1 timer interrupt enabled
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 8 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.3.2.1 interrupt output bits tf and af: when an alarm occurs, af is set to logic 1. similarly, at the end of a timer countdown, tf is set to logic 1. these bi ts maintain their value until overwritten using the interface. if both timer and alarm interrupts are required in the application, the source of the interrupt can be determined by reading these bits. to prevent one flag being overwritten while clearing another, a logic and is performed during a write access. bits tie and aie: these bits activate or deactivate the generation of an interrupt when tf or af is asserted, respective ly. the interrupt is the logica l or of these two conditions when both aie and tie are set. countdown timer interrupts: the pulse generator for the countdown timer interrupt uses an internal clock and is dependent on the selected source clock for the countdown timer and on the countdown value n. as a consequence, the width of the interrupt pulse varies (see table 7 ). [1] tf and int become active simultaneously. [2] n = loaded countdown value. timer stops when n = 0. when bits tie and aie are disabled, pin int will remain high-impedance. fig 6. interrupt scheme 013aaa087 te countdown counter af: alarm flag clear set to interface: read af 0 1 tf: timer clear set pulse generator 2 clear trigger tie int from interface: clear tf from interface: clear af set alarm flag af to interface: read tf ti_tp aie e.g. aie 0 1 table 7. int operation (bit ti_tp = 1) [1] source clock (hz) int period (s) n=1 [2] n>1 [2] 4096 1 8192 1 4096 64 1 128 1 64 1 1 64 1 64 1 60 1 64 1 64
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 9 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.4 time and date registers the majority of the registers are coded in the bcd format to simplify application use. 8.4.1 register vl_seconds [1] start-up value. 8.4.1.1 voltage-low detector and clock monitor the pcf8563 has an on-chip voltage-low detector (see figure 7 ). when v dd drops below v low , bit vl in the vl_seconds register is set to indicate that the integrity of the clock information is no longer guaranteed. the vl flag can only be cleared by using the interface. table 8. vl_seconds - seconds and clock integrity status register (address 02h) bit description bit symbol value place value description 7 vl 0 - clock integrity is guaranteed 1 [1] - integrity of the clock information is not guaranteed 6 to 4 seconds 0 to 5 ten?s place actual seconds coded in bcd format, see ta b l e 9 3 to 0 0 to 9 unit place table 9. seconds coded in bcd format seconds value (decimal) upper-digit (ten?s place) digit (unit place) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 0000000 01 0000001 02 0000010 : ::::::: 09 0001001 10 0010000 : ::::::: 58 1011000 59 1011001 fig 7. voltage-low detection vl set normal power operation period of battery operation t v dd v low mgr887
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 10 of 45 nxp semiconductors pcf8563 real-time clock/calendar the vl flag is intended to detect the situation when v dd is decreasing slowly, for example under battery o peration. should the os cillator stop or v dd reach v low before power is re-asserted, th en the vl flag is set. this will indi cate that the time may be corrupted. 8.4.2 register minutes 8.4.3 register hours 8.4.4 register days [1] the pcf8563 compensates for leap years by adding a 29 th day to february if the year counter contains a value which is exactly divisi ble by 4, including the year 00. 8.4.5 register weekdays table 10. minutes - minutes register (address 03h) bit description bit symbol value place value description 7 - - - unused 6 to 4 minutes 0 to 5 ten?s place actual minutes coded in bcd format 3 to 0 0 to 9 unit place table 11. hours - hours register (address 04h) bit description bit symbol value place value description 7 to 6 - - - unused 5 to 4 hours 0 to 2 ten?s place actual hours coded in bcd format 3to0 0to9 unit place table 12. days - days register (address 05h) bit description bit symbol value place value description 7 to 6 - - - unused 5to4 days [1] 0 to 3 ten?s place actual day coded in bcd format 3to0 0to9 unit place table 13. weekdays - weekdays register (address 06h) bit description bit symbol value description 7 to 3 - - unused 2 to 0 weekdays 0 to 6 actual weekday values, see ta b l e 1 4
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 11 of 45 nxp semiconductors pcf8563 real-time clock/calendar [1] definition may be re-assigned by the user. 8.4.6 register century_months [1] this bit may be re-assigned by the user. [2] this bit is toggled when the regist er years overflows from 99 to 00. table 14. weekday assignments day [1] bit 2 1 0 sunday 0 0 0 monday 0 0 1 tuesday 0 1 0 wednesday 0 1 1 thursday 1 0 0 friday 1 0 1 saturday110 table 15. century_months - century flag and months register (address 07h) bit description bit symbol value place value description 7c [1] 0 [2] - indicates the century is x 1 - indicates the century is x + 1 6 to 5 - - - unused 4 months 0 to 1 ten?s place actual month coded in bcd format, see table 16 3 to 0 0 to 9 unit place table 16. month assignments in bcd format month upper-digit (ten?s place) digit (unit place) bit 4 bit 3 bit 2 bit 1 bit 0 january 0 0 0 0 1 february 0 0 0 1 0 march 0 0 0 1 1 april00100 may00101 june00110 july00111 august01000 september 0 1 0 0 1 october10000 november10001 december10010
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 12 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.4.7 register years [1] when the register years overflows from 99 to 00, t he century bit c in the register century_months is toggled. 8.5 setting and reading the time figure 8 shows the data flow and data dependenci es starting from the 1 hz clock tick. during read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. this prevents ? faulty reading of the clock and calendar during a carry condition ? incrementing the time registers, during the read cycle after this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read access is serviced. a maximum of 1 request can be st ored; therefore, all accesses must be completed within 1 second (see figure 9 ). table 17. years - years register (08h) bit description bit symbol value place value description 7 to 4 years 0 to 9 ten?s place actual year coded in bcd format [1] 3to0 0to9 unit place fig 8. data flow for the time function 013aaa092 1 hz tick weekday seconds minutes hours days leap year calculation months years c
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 13 of 45 nxp semiconductors pcf8563 real-time clock/calendar as a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. failing to comply with this method co uld result in the time becoming corrupted. as an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. a similar problem exists when reading. a roll over may occur between reads thus giving the minutes from one moment and the hours from the next. recommended method for reading the time: 1. send a start condition and the slave address for write (a2h). 2. set the address pointer to 2 (vl_seconds) by sending 02h. 3. send a restart condition or stop followed by start. 4. send the slave address for read (a3h). 5. read vl_seconds. 6. read minutes. 7. read hours. 8. read days. 9. read weekdays. 10. read century_months. 11. read years. 12. send a stop condition. fig 9. access time for read/write operations t < 1 s 013aaa215 slave address data stop data start
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 14 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.6 alarm registers 8.6.1 register minute_alarm [1] default value. 8.6.2 register hour_alarm [1] default value. 8.6.3 register day_alarm [1] default value. 8.6.4 register weekday_alarm [1] default value. table 18. minute_alarm - minute alarm register (address 09h) bit description bit symbol value place value description 7 ae_m 0 - minute alarm is enabled 1 [1] - minute alarm is disabled 6 to 4 minute_alarm 0 to 5 ten?s place minute alarm information coded in bcd format 3 to 0 0 to 9 unit place table 19. hour_alarm - hour alarm regist er (address 0ah) bit description bit symbol value place value description 7 ae_h 0 - hour alarm is enabled 1 [1] - hour alarm is disabled 6 - - - unused 5 to 4 hour_alarm 0 to 2 ten?s place hour alarm information coded in bcd format 3 to 0 0 to 9 unit place table 20. day_alarm - day alarm register (address 0bh) bit description bit symbol value place value description 7 ae_d 0 - day alarm is enabled 1 [1] - day alarm is disabled 6 - - - unused 5 to 4 day_alarm 0 to 3 ten?s place day alarm information coded in bcd format 3 to 0 0 to 9 unit place table 21. weekday_alarm - weekday alarm re gister (address 0ch) bit description bit symbol value description 7 ae_w 0 weekday alarm is enabled 1 [1] weekday alarm is disabled 6 to 3 - - unused 2 to 0 weekday_alarm 0 to 6 weekday alarm information
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 15 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.6.5 alarm flag by clearing the alarm enable bit (ae_x) of one or more of the alarm registers, the corresponding alarm condition(s) are active. when an alarm occurs, af is set to logic 1. the asserted af can be used to generate an interrupt (int ). the af is cleared using the interface. the registers at addresses 09h through 0ch contain alarm information. when one or more of these registers is loaded with minute, hour, day or weekday, and its corresponding ae_x is logic 0, then that info rmation is compared with the current minute, hour, day, and weekday. when all enabled comparisons first match, the alarm flag (af in register control_2) is set to logic 1. the generation of interrupts from the alarm func tion is controlled via bit aie. if bit aie is enabled, the int pin follows the condition of bit af. af will remain set until cleared by the interface. once af has been cleared, it will only be set aga in when the time increments to match the alarm condition once more. alarm re gisters which have their ae_x bit at logic 1 are ignored. 8.7 register clkout_control and clock output frequencies of 32.768 khz ( default), 1.024 khz, 32 hz, and 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. (1) only when all enabled alarm settings are matching. it?s only on increment to a matched case that the alarm flag is set, see section 8.6.5 . fig 10. alarm function block diagram 013aaa088 weekday alarm ae_w weekday time = day alarm ae_d day time = hour alarm ae_h hour time = minute alarm ae_m minute time = check now signal set alarm flag af (1) ae_m = 1 1 0 example
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 16 of 45 nxp semiconductors pcf8563 real-time clock/calendar [1] default value. 8.8 timer function the 8-bit countdown timer at address 0fh is controlled by the timer_control register at address 0eh. the timer_control register determines one of 4 source clock frequencies for the timer (4096 hz, 64 hz, 1 hz, or 1 60 hz), and enables or disables the timer. the timer counts down from a software-loaded 8-bit binary value. at the end of every countdown, the timer sets the timer flag tf. the tf may only be cleared by using the interface. the asserted tf can be used to generate an interrupt on pin int . the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the state of tf. bit ti_tp is used to control this mode selection. when reading the timer, the current countdown value is returned. 8.8.1 register timer_control [1] default value. [2] these bits determine the source clock for the countdow n timer; when not in use, td[1:0] should be set to 1 60 hz for power saving. table 22. clkout_control - clkout control register (address 0dh) bit description bit symbol value description 7 fe 0 the clkout output is inhi bited and clkout output is set to logic 0 1 [1] the clkout output is activated 6 to 2 - - unused 1 to 0 fd[1:0] frequency output at pin clkout 00 [1] 32.768 khz 01 1.024 khz 10 32 hz 11 1 hz table 23. timer_control - timer control register (address 0eh) bit description bit symbol value description 7te 0 [1] timer is disabled 1 timer is enabled 6 to 2 - - unused 1 to 0 td[1:0] timer source clock frequency select [2] 00 4.096 khz 01 64 hz 10 1 hz 11 [2] 1 60 hz
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 17 of 45 nxp semiconductors pcf8563 real-time clock/calendar 8.8.2 register timer the register timer is an 8-bit binary countdow n timer. it is enabled and disabled via the timer_control register bit te. the source clock for the timer is also selected by the timer_control register. other timer properties such as interrupt generation are controlled via the register control_status _ 2. for accurate read back of the count down va lue, it is recommended to read the register twice and check for consistent results, since it is not possible to freeze the countdown timer counter during read back. 8.9 ext_clk test mode a test mode is available which allo ws for on-board testing. in such a mode it is possible to set up test conditions and control the operation of the rtc. the test mode is entered by setting bit t est1 in register control_status_1. then pin clkout becomes an input. the test mode replaces the internal 64 hz signal with the signal applied to pin clkout. every 64 posi tive edges applied to pin clkout will then generate an increment of one second. the signal applied to pin clkout should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. the internal 64 hz clock, now source d from clkout, is divided down to 1 hz by a 2 6 divide chain called a prescaler. the prescaler can be set into a known state by using bit stop. when bit stop is set, the prescaler is reset to 0 (stop must be cleared before the prescaler can operate again). from a stop condition, the first 1 second increment will take place after 32 positive edges on clkout. thereafter, every 64 positive edges will cause a one-second increment. remark: entry into ext_clk test mode is not syn chronized to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the prescaler can be made. 8.9.1 operation example: 1. set ext_clk test mode (con trol_status_1, bit test1 = 1). 2. set stop (control_status_1, bit stop = 1). 3. clear stop (control_status_1, bit stop = 0). 4. set time registers to desired value. table 24. timer - timer value regist er (address 0fh) bit description bit symbol value description 7 to 0 timer[7:0] 00h to ffh countdown period in seconds: where n is the countdown value table 25. timer register bits value range bit 7 6 5 4 3 2 1 0 1286432168421 countdownperiod n sourceclockfrequency -------------------------------------------------------------- - =
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 18 of 45 nxp semiconductors pcf8563 real-time clock/calendar 5. apply 32 clock pulses to clkout. 6. read time registers to see the first change. 7. apply 64 clock pulses to clkout. 8. read time registers to see the second change. repeat steps 7 and 8 for additional increments. 8.10 stop bit function the function of the stop bit is to allow for accurate starting of the time circuits. the stop bit function will caus e the upper part of the prescaler (f 2 to f 14 ) to be held in reset and thus no 1 hz ticks will be generated (see figure 11 ). the time circuits can then be set and will not increment until the stop bit is released (see figure 12 and ta b l e 2 6 ). the stop bit function will not af fect the output of 32.768 khz on clkout, but will stop the generation of 1.024 khz, 32 hz, and 1 hz. the lower two stages of the prescaler (f 0 and f 1 ) are not reset; and because the i 2 c-bus is asynchronous to the crystal oscillator, the ac curacy of re-starting the time circuits will be between zero and one 8.192 khz cycle (see figure 12 ). fig 11. stop bit functional diagram 013aaa089 oscillator 32768 hz 16384 hz oscillator stop detector f 0 f 1 f 13 reset f 14 reset f 2 reset 2 hz 1024 hz 32 hz 1 hz tick stop clkout source reset 8192 hz 4096 hz 32768 hz 1 hz fig 12. stop bit release timing 001aaf912 8192 hz stop released 0 s to 122 s
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 19 of 45 nxp semiconductors pcf8563 real-time clock/calendar [1] f 0 is clocked at 32.768 khz. the first increment of the time circuits is between 0.507813 s and 0.507935 s after stop bit is released. the uncertainty is caused by the prescaler bits f 0 and f 1 not being reset (see table 26 ) and the unknown state of the 32 khz clock. 8.11 reset the pcf8563 includes an internal reset circuit which is active whenever the oscillator is stopped. in the reset state the i 2 c-bus logic is initialized including the address pointer and all registers are set according to ta b l e 2 7 . i 2 c-bus communication is not possible during reset. table 26. first increment of time circuits after stop bit release bit prescaler bits [1] 1hz tick time comment stop f 0 f 1 -f 2 to f 14 hh:mm:ss clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally stop bit is activated by user. f 0 f 1 are not reset and values cannot be predicted externally 1 xx-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xx-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen stop bit is released by user 0 xx-0 0000 0000 0000 08:00:00 prescaler is now running xx-1 0000 0000 0000 08:00:00 - xx-0 1000 0000 0000 08:00:00 - xx-1 1000 0000 0000 08:00:00 - : :: 11-1 1111 1111 1110 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of f 14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : :: 11-1 1111 1111 1111 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : :: 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of f 14 increments the time circuits 013aaa076 0.507813 to 0.507935 s 1.000000 s
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 20 of 45 nxp semiconductors pcf8563 real-time clock/calendar [1] registers marked x are undefined at power-up and unchanged by subsequent resets. 8.11.1 power-on reset (por) override the por duration is directly rela ted to the crystal o scillator start-up time. due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the por and hence speed up on-board test of the device. the setting of this mode requires that the i 2 c-bus pins, sda and scl, are toggled in a specific order as shown in figure 13 . all timings are required minimums. once the override mode has been entered, the device immediately stops, being reset, and normal operation may commence i.e. en try into the ext_clk test mode via i 2 c-bus access. the override mode may be cleared by writing logic 0 to testc. testc must be set to logic 1 before re-entry into the overri de mode is possible. setting testc to logic 0 during normal operation has no effect except to prevent entry into the por override mode. table 27. register reset value [1] address register name bit 7 6 5 4 3 2 1 0 00h control_status_100001000 01h control_status_200000000 02h vl_seconds 1xxxxxxx 03h minutes xxxxxxxx 04h hours xxxxxxxx 05h days xxxxxxxx 06h weekdays xxxxxxxx 07h century_monthsxxxxxxxx 08h years xxxxxxxx 09h minute_alarm 1xxxxxxx 0ahhour_alarm 1xxxxxxx 0bhday_alarm 1xxxxxxx 0chweekday_alarm1xxxxxxx 0dhclkout_control1xxxxx00 0ehtimer_control 0xxxxx11 0fhtimer xxxxxxxx fig 13. por override sequence mgm664 scl 500 ns 2000 ns sda 8 ms override active power-on
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 21 of 45 nxp semiconductors pcf8563 real-time clock/calendar 9. characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see figure 14 ). 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition - s. a low-to-high transition of the data line while the clock is high is defined as the stop condition - p (see figure 15 ). 9.3 system configuration a device generating a message is a transm itter; a device receiving a message is a receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves (see figure 16 ). fig 14. bit transfer mbc621 data line stable; data valid change of data allowed sda scl fig 15. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 22 of 45 nxp semiconductors pcf8563 real-time clock/calendar 9.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlim ited. each byte of eight bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. acknowledgement on the i 2 c-bus is illustrated in figure 17 . fig 16. system configuration mba605 master transmitter receiver slave receiver slave transmitter receiver master transmitter master transmitter receiver sda scl fig 17. acknowledgement on the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 23 of 45 nxp semiconductors pcf8563 real-time clock/calendar 9.5 i 2 c-bus protocol 9.5.1 addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always ca rried out with the first byte transmitted after the start procedure. the pcf8563 acts as a slave receiver or slav e transmitter. therefore the clock signal scl is only an input signal, but the data signal sda is a bidirectional line. two slave addresses are reserved for the pcf8563: read: a3h (10100011) write: a2h (10100010) the pcf8563 slav e address is illustrated in figure 18 . 9.5.2 clock and calendar read or write cycles the i 2 c-bus configuration for the different pcf 8563 read and write cycles is shown in figure 19 , figure 20 and figure 21 . the register address is a 4-bit value that defines which register is to be accessed next. the uppe r four bits of the register address are not used. fig 18. slave address mce189 1 0 1 0 0 0 1 r/w group 1 group 2 fig 19. master transmits to slave receiver (write mode) s 0a slave address register address a a data p acknowledgement from slave acknowledgement from slave acknowledgement from slave r/w auto increment memory register address 013aaa346 n bytes
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 24 of 45 nxp semiconductors pcf8563 real-time clock/calendar (1) at this moment master transmitter becomes master re ceiver and pcf8563 slave receiv er becomes slave transmitter. fig 20. master reads after setting register address (write register address; read data) s 0a slave address register address a a r/w a data 013aaa041 p 1 auto increment memory register address last byte r/w s1 n bytes (1) acknowledgement from slave acknowledgement from slave acknowledgement from slave acknowledgement from slave no acknowledgement from master auto increment memory register address slave address data fig 21. master reads slave immediatel y after first byte (read mode) s 1a slave address data a1 data acknowledgement from slave acknowledgement from master no acknowledgement from master r/w auto increment register address 013aaa347 auto increment register address n bytes last byte p
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 25 of 45 nxp semiconductors pcf8563 real-time clock/calendar 9.6 interface watchdog timer during read/write operations, the time counting circuits are frozen. to prevent a situation where the accessing device becomes locked and does not clear the interface, the pcf8563 has a built in watchdog timer. should the interface be active for more than 1 s from the time a valid slave address is transm itted, then the pcf8563 will automatically clear the interface and allow the time counting circuits to continue counting. the watchdog will trigger between 1 s and 2 s after receivin g a valid slave address. each time the watchdog period is exceeded, 1 s will be lost from the time counters. the watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is remove d from a battery backed-up system during an interface access. a. correct data transfer: read or write b. incorrect data transfer; read or write fig 22. interface watchdog timer 013aaa420 slave address running time counters wd timer data wd timer tracking time counters frozen running data t < 1 s data stop start 013aaa421 slave address running time counters wd timer data wd timer tracking time counters frozen running data 1 s < t < 2 s data start data transfer fail wd trips
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 26 of 45 nxp semiconductors pcf8563 real-time clock/calendar 10. internal circuitry fig 23. device diode protection diagram 013aaa348 sda v ss scl int clkout osco v dd osci pcf8563
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 27 of 45 nxp semiconductors pcf8563 real-time clock/calendar 11. limiting values [1] pass level; human body model (hbm), according to ref. 5 ? jesd22-a114 ? . [2] pass level; charged-device model (cdm), according to ref. 6 ? jesd22-c101 ? . [3] pass level; latch-up testing according to ref. 7 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the nxp store and transport requirements (see ref. 9 ? nx3-00092 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. for long term storage produc ts deviant conditions are described in that document. table 28. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v i dd supply current ? 50 +50 ma v i input voltage on pins scl, sda, and osci ? 0.5 +6.5 v v o output voltage on pins clkout and int ? 0.5 +6.5 v i i input current at any input ? 10 +10 ma i o output current at any output ? 10 +10 ma p tot total power dissipation - 300 mw v esd electrostatic discharge voltage hbm hvson10 (pcf8563bs/4) [1] - ? 3500 v dip8 (pcf8563p/f4) [1] so8 (pcf8563t/f4) [1] tssop8 (pcf8563ts/4) [1] so8 (pcf8563t/5) [1] - ? 2000 v tssop8 (pcf8563ts/5) [1] cdm hvson10 (pcf8563bs/4) [2] - ? 2000 v dip8 (pcf8563p/f4) [2] - ? 500 v so8 (pcf8563t/f4) [2] - ? 1000 v so8 (pcf8563t/5) [2] - ? 1500 v tssop8 (pcf8563ts/4) [2] - ? 1500 v tssop8 (pcf8563ts/5) [2] - ? 1750 v i lu latch-up current [3] -2 0 0m a t stg storage temperature [4] ? 65 +150 ? c t amb ambient temperature operating device ? 40 +85 ? c
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 28 of 45 nxp semiconductors pcf8563 real-time clock/calendar 12. static characteristics table 29. static characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 8 pf; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage interface inactive; f scl =0hz; t amb =25 ?c [1] 1.0 - 5.5 v interface active; f scl = 400 khz [1] 1.8 - 5.5 v clock data integrity; t amb =25 ?c v low -5.5v i dd supply current interface active f scl =400khz --800 ? a f scl =100khz --200 ? a interface inactive (f scl = 0 hz); clkout disabled; t amb =25 ?c [2] v dd = 5.0 v - 275 550 na v dd = 3.0 v - 250 500 na v dd = 2.0 v - 225 450 na interface inactive (f scl = 0 hz); clkout disabled; t amb = ? 40 ? cto +85 ?c [2] v dd = 5.0 v - 500 750 na v dd = 3.0 v - 400 650 na v dd = 2.0 v - 400 600 na interface inactive (f scl = 0 hz); clkout enabled at 32 khz; t amb =25 ?c [2] v dd = 5.0 v - 825 1600 na v dd = 3.0 v - 550 1000 na v dd = 2.0 v - 425 800 na interface inactive (f scl = 0 hz); clkout enabled at 32 khz; t amb = ? 40 ? cto +85?c [2] v dd = 5.0 v - 950 1700 na v dd = 3.0 v - 650 1100 na v dd = 2.0 v - 500 900 na inputs v il low-level input voltage v ss -0.3v dd v v ih high-level input voltage 0.7v dd -v dd v i li input leakage current v i =v dd or v ss ? 10 +1 ? a c i input capacitance [3] --7pf
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 29 of 45 nxp semiconductors pcf8563 real-time clock/calendar [1] for reliable oscillator start-up at power-up: v dd(min)power-up =v dd(min) +0.3v. [2] timer source clock = 1 60 hz, level of pins scl and sda is v dd or v ss . [3] tested on sample basis. outputs i ol low-level output current output sink current; v ol =0.4v; v dd =5v on pin sda 3 - - ma on pin int 1- - ma on pin clkout 1 - - ma i lo output leakage current v o =v dd or v ss ? 10 +1 ? a voltage detector v low low voltage t amb =25 ? c; sets bit vl; see figure 7 -0.91.0v table 29. static characteristics ?continued v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 8 pf; unless otherwise specified. symbol parameter conditions min typ max unit t amb =25 ? c; timer = 1 minute. t amb =25 ? c; timer = 1 minute. fig 24. supply current i dd as a function of supply voltage v dd ; clkout disabled fig 25. supply current i dd as a function of supply voltage v dd ; clkout = 32 khz 02 6 mgr888 4 v dd (v) 1 0 0.4 0.2 0.8 0.6 i dd (a) 02 6 mgr889 4 v dd (v) 1 0 0.4 0.2 0.8 0.6 i dd (a)
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 30 of 45 nxp semiconductors pcf8563 real-time clock/calendar v dd = 3 v; timer = 1 minute. t amb =25 ? c; normalized to v dd =3v. fig 26. supply current i dd as a function of temperature t; clkout = 32 khz fig 27. frequency deviation as a function of supply voltage v dd ? 40 0 40 120 mgr890 80 t (c) 1 0 0.4 0.2 0.8 0.6 i dd (a) 02 6 4 2 ?4 ?2 0 mgr891 4 v dd (v) frequency deviation (ppm)
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 31 of 45 nxp semiconductors pcf8563 real-time clock/calendar 13. dynamic characteristics [1] c l is a calculation of c trim and c osco in series: . [2] unspecified for f clkout = 32.768 khz. [3] all timing values are valid within the operating supply voltage at ambient temperature and referenced to v il and v ih with an input voltage swing of v ss to v dd . [4] a detailed description of the i 2 c-bus specification is given in ref. 11 ? um10204 ? . [5] i 2 c-bus access time between two starts or between a start and a stop condition to this device must be less than one second. table 30. dynamic characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =40k ? ; c l = 8 pf; unless otherwise specified. symbol parameter conditions min typ max unit oscillator c osco capacitance on pin osco 15 25 35 pf ? f osc /f osc relative oscillator frequency variation ? v dd =200mv; t amb =25 ?c -0.2-ppm quartz crystal parameters (f = 32.768 khz) r s series resistance - - 100 k ? c l load capacitance parallel [1] 7 - 12.5 pf c trim trimmer capacitance external; on pin osci 5- 25pf clkout output ? clkout duty cycle on pin clkout [2] -50-% i 2 c-bus timing char acteristics (see figure 28 ) [3] [4] f scl scl clock frequency [5] - - 400 khz t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s t r rise time of both sda and scl signals standard-mode - - 1 ? s fast-mode - - 0.3 ? s t f fall time of both sda and scl signals - - 0.3 ? s c b capacitive load for each bus line - - 400 pf t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - ? s t w(spike) spike pulse width on bus - - 50 ns c l c trim c osco ? ?? c trim c osco + ?? ----------------------------------------- =
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 32 of 45 nxp semiconductors pcf8563 real-time clock/calendar 14. application information fig 28. i 2 c-bus timing waveforms sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat fig 29. application diagram mgm665 scl sda v ss osci osco clock calendar pcf8563 sda scl master transmitter/ receiver v dd v dd sda scl rr v dd (i 2 c-bus) r: pull-up resistor r = 1 f t r c b 100 nf
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 33 of 45 nxp semiconductors pcf8563 real-time clock/calendar 14.1 quartz frequency adjustment 14.1.1 method 1: fixed osci capacitor by evaluating the average capacitance necessary for the application layout, a fixed capacitor can be used. the frequency is best measured via the 32.768 khz signal available after power-on at pin clkout. the frequency tolerance depends on the quartz crystal tolerance, the capacitor tolerance and the device-to-device tolerance (on average ? 5 ppm). average deviations of ? 5 minutes per year can be easily achieved. 14.1.2 method 2: osci trimmer using the 32.768 khz signal available after po wer-on at pin clkout, fast setting of a trimmer is possible. 14.1.3 method 3: osco output direct measurement of osco out (accounting for test probe capacitance).
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 34 of 45 nxp semiconductors pcf8563 real-time clock/calendar 15. package outline fig 30. package outline sot650-1 (hvson10) of pcf8563bs 0.5 0.2 1 0.05 0.00 a 1 e h b unit d (1) y e 2 e 1 references outline version european projection issue date iec jedec jeita mm 3.1 2.9 cd h 1.75 1.45 y 1 3.1 2.9 2.55 2.15 0.30 0.18 0.05 0.1 dimensions (mm are the original dimensions) sot650-1 mo-229 - - - - - - e (1) 0.55 0.30 l 0.1 v 0.05 w 0 2 mm 1 scale sot650-1 hvson10: plastic thermal enhanced very thin small outline package; no leads; 10 terminals; body 3 x 3 x 0.85 mm a (1) max. a a 1 c detail x y d h e h e l 10 5 1 6 d e y 1 c c b a 01-01-22 02-02-08 terminal 1 index area terminal 1 index area x e 1 b ac c b v m w m note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included.
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 35 of 45 nxp semiconductors pcf8563 real-time clock/calendar fig 31. package outline sot97-1 (dip8) of pcf8563p references outline version european projection issue date iec jedec jeita sot97-1 99-12-27 03-02-13 unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.14 0.53 0.38 0.36 0.23 9.8 9.2 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 1.15 4.2 0.51 3.2 inches 0.068 0.045 0.021 0.015 0.014 0.009 1.07 0.89 0.042 0.035 0.39 0.36 0.26 0.24 0.14 0.12 0.01 0.1 0.3 0.32 0.31 0.39 0.33 0.045 0.17 0.02 0.13 b 2 050g01 mo-001 sc-504-8 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 8 1 5 4 b e 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. pin 1 index dip8: plastic dual in-line package; 8 leads (300 mil) sot97-1
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 36 of 45 nxp semiconductors pcf8563 real-time clock/calendar fig 32. package outline sot96-1 (so8) of pcf8563t unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 1.0 0.4 sot96-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.05 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 99-12-27 03-02-18
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 37 of 45 nxp semiconductors pcf8563 real-time clock/calendar fig 33. package outline sot505-1 (tssop8) of pcf8563ts unit a 1 a max. a 2 a 3 b p lh e l p wy v ce d (1) e (2) z (1) references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.70 0.35 6 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.4 sot505-1 99-04-09 03-02-18 w m b p d z e 0.25 14 8 5 a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1 1.1 pin 1 index
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 38 of 45 nxp semiconductors pcf8563 real-time clock/calendar 16. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 39 of 45 nxp semiconductors pcf8563 real-time clock/calendar 17.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 34 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 3 1 and 32 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 34 . table 31. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 32. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 40 of 45 nxp semiconductors pcf8563 real-time clock/calendar for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 18. abbreviations msl: moisture sensitivity level fig 34. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 33. abbreviations acronym description bcd binary coded decimal cdm charged-device model cmos complementary metal oxide semiconductor esd electrostatic discharge hbm human body model i 2 c inter-integrated circuit ic integrated circuit lsb least significant bit msb most significant bit msl moisture sensitivity level pcb printed-circuit board por power-on reset rtc real-time clock scl serial clock line sda serial data line smd surface mount device
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 41 of 45 nxp semiconductors pcf8563 real-time clock/calendar 19. references [1] an10365 ? surface mount reflow soldering description [2] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [3] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [4] ipc/jedec j-std-020 ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [5] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [6] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [7] jesd78 ? ic latch-up test [8] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [9] nx3-00092 ? nxp store and transport requirements [10] snv-fa-01-02 ? marking formats integrated circuits [11] um10204 ? i 2 c-bus specification and user manual
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 42 of 45 nxp semiconductors pcf8563 real-time clock/calendar 20. revision history table 34. revision history document id release date data sheet status change notice supersedes pcf8563 v.9 20110616 product data sheet - pcf8563 v.8 modifications: ? added design-in and replacement part information pcf8563 v.8 20101118 product data sheet - pcf8563 v.7 pcf8563 v.7 20100723 product data sheet - pcf8563_6 pcf8563_6 20080221 product data sheet - pcf8563_5 pcf8563_5 20070717 product data sheet - pcf8563-04 pcf8563-04 (9397 750 12999) 20040312 product data - pcf8563-03 pcf8563-03 (9397 750 11158) 20030414 product data - pcf8563-02 pcf8563-02 (9397 750 04855) 19990416 product data - pcf8563_n_1 pcf8563_n_1 (9397 750 03282) 19980325 objective specification - -
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 43 of 45 nxp semiconductors pcf8563 real-time clock/calendar 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 21.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 21.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcf8563 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 9 ? 16 june 2011 44 of 45 nxp semiconductors pcf8563 real-time clock/calendar non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 21.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcf8563 real-time clock/calendar ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 16 june 2011 document identifier: pcf8563 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 5 8.1 clkout output . . . . . . . . . . . . . . . . . . . . . . . . 5 8.2 register organization . . . . . . . . . . . . . . . . . . . . 6 8.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3.1 register control_status_1 . . . . . . . . . . . . . . . . 7 8.3.2 register control_status_2 . . . . . . . . . . . . . . . . 7 8.3.2.1 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.4 time and date registers . . . . . . . . . . . . . . . . . . 9 8.4.1 register vl_seconds . . . . . . . . . . . . . . . . . . . . 9 8.4.1.1 voltage-low detector and clock monitor . . . . . . 9 8.4.2 register minutes. . . . . . . . . . . . . . . . . . . . . . . 10 8.4.3 register hours . . . . . . . . . . . . . . . . . . . . . . . . 10 8.4.4 register days . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.4.5 register weekdays. . . . . . . . . . . . . . . . . . . . . 10 8.4.6 register century_months . . . . . . . . . . . . . . . . 11 8.4.7 register years . . . . . . . . . . . . . . . . . . . . . . . . 12 8.5 setting and reading the time. . . . . . . . . . . . . . 12 8.6 alarm registers . . . . . . . . . . . . . . . . . . . . . . . . 14 8.6.1 register minute_alarm . . . . . . . . . . . . . . . . . . 14 8.6.2 register hour_alarm . . . . . . . . . . . . . . . . . . . 14 8.6.3 register day_alarm . . . . . . . . . . . . . . . . . . . . 14 8.6.4 register weekday_alarm . . . . . . . . . . . . . . . . 14 8.6.5 alarm flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.7 register clkout_control and clock output. . 15 8.8 timer function . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.8.1 register timer_control . . . . . . . . . . . . . . . . . . 16 8.8.2 register timer . . . . . . . . . . . . . . . . . . . . . . . . 17 8.9 ext_clk test mode . . . . . . . . . . . . . . . . . . . . 17 8.9.1 operation example: . . . . . . . . . . . . . . . . . . . . 17 8.10 stop bit function . . . . . . . . . . . . . . . . . . . . . . 18 8.11 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.11.1 power-on reset (por) override . . . . . . . . . . 20 9 characteristics of the i 2 c-bus . . . . . . . . . . . . 21 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.2 start and stop conditions . . . . . . . . . . . . . 21 9.3 system configuration . . . . . . . . . . . . . . . . . . . 21 9.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.5 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23 9.5.1 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5.2 clock and calendar read or write cycles . 23 9.6 interface watchdog timer . . . . . . . . . . . . . . . . 25 10 internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 26 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27 12 static characteristics . . . . . . . . . . . . . . . . . . . 28 13 dynamic characteristics. . . . . . . . . . . . . . . . . 31 14 application information . . . . . . . . . . . . . . . . . 32 14.1 quartz frequency adjustment. . . . . . . . . . . . . 33 14.1.1 method 1: fixed osci capa citor . . . . . . . . . . . 33 14.1.2 method 2: osci trimmer . . . . . . . . . . . . . . . . 33 14.1.3 method 3: osco output . . . . . . . . . . . . . . . . 33 15 package outline. . . . . . . . . . . . . . . . . . . . . . . . 34 16 handling information . . . . . . . . . . . . . . . . . . . 38 17 soldering of smd packages . . . . . . . . . . . . . . 38 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 38 17.2 wave and reflow soldering. . . . . . . . . . . . . . . 38 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 39 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 39 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40 19 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20 revision history . . . . . . . . . . . . . . . . . . . . . . . 42 21 legal information . . . . . . . . . . . . . . . . . . . . . . 43 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 43 21.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 43 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 44 22 contact information . . . . . . . . . . . . . . . . . . . . 44 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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